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| VND810PEP-E DOUBLE CHANNEL HIGH SIDE DRIVER TARGET SPECIFICATION Table 1. General Features TYPE VND810PEP-E (*) Per each channel Figure 1. Package IOUT 3.5 A (*) VCC 36 V RDS(on) 160 m (*) CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS ON STATE OPEN LOAD DETECTION OFF STATE OPEN LOAD DETECTION SHORTED LOAD PROTECTION UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN PROTECTION AGAINST LOSS OF GROUND VERY LOW STAND-BY CURRENT REVERSE BATTERY PROTECTION (**) IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE PowerSSO-12 DESCRIPTION The VND810PEP-E is a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. Table 2. Order Codes Package PowerSSO-12 Note: (**) See application schematic at page 9 Tube VND810PEP-E Tape and Reel VND810PEPTR-E Rev. 4 November 2004 1/15 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. VND810PEP-E Figure 2. Block Diagram Vcc Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE GND INPUT1 STATUS1 CLAMP 1 OUTPUT1 DRIVER 1 CLAMP 2 CURRENT LIMITER 1 LOGIC OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 DRIVER 2 OUTPUT2 INPUT2 OPENLOAD OFF 1 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 OPENLOAD ON 2 Table 3. Absolute Maximum Ratings Symbol VCC - VCC - IGND IOUT - IOUT IIN Istat DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human R=1.5K; C=100pF) VESD - INPUT - STATUS - OUTPUT - VCC Ptot Tj Tc Tstg Power Dissipation TC=25C Junction Operating Temperature Case Operating Temperature Storage Temperature Body Model: 4000 4000 5000 5000 54 Internally Limited - 40 to 150 - 55 to 150 V V V V W C C C Parameter Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 Unit V V mA A A mA mA 2/15 VND810PEP-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins GND NC INPUT1 STATUS1 STATUS2 INPUT2 1 2 3 4 5 6 12 11 10 9 8 7 Vcc OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 Vcc TAB = Vcc Connection / Pin Status Floating X To Ground N.C. X X Output X Input X Through 10K resistor Figure 4. Current and Voltage Conventions IS VF1 (*) IIN1 INPUT 1 VIN1 VSTAT1 ISTAT1 STATUS 1 IIN2 INPUT 2 VIN2 ISTAT2 STATUS 2 VSTAT2 GND IGND OUTPUT 2 OUTPUT 1 VCC VCC IOUT1 VOUT1 IOUT2 VOUT2 (*) VFn = VCCn - VOUTn during reverse battery condition Table 4. Thermal Data Symbol Rthj-case Rthj-amb Parameter Thermal resistance junction-case Thermal resistance junction-ambient (MAX) (MAX) Value 2.3 61 (*) 50 (**) Unit C/W C/W Note: (*) When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35m thick) connected to all V CC pins. Note: (**) When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35m thick) connected to all V CC pins. 3/15 VND810PEP-E ELECTRICAL CHARACTERISTICS (8V IS Supply Current Tj=25C On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V VIN=0V; VOUT =3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C IL(off1) IL(off2) IL(off3) IL(off4) Off State Output Current Off State Output Current Off State Output Current Off State Output Current Table 6. Switching (VCC =13V) Symbol td(on) td(off) (dVOUT / dt)on (dVOUT / dt)off Parameter Turn-on delay time Turn-on delay time Test Conditions RL=13 from VIN rising edge to VOUT =1.3V RL=13 from VIN falling edge to VOUT =11.7V RL=13 from VOUT=1.3V to VOUT =10.4V RL=13 from VOUT=11.7V to VOUT =1.3V Min. Typ. 30 30 See relative diagram See relative diagram Max. Unit s s Turn-on voltage slope V/s Turn-off voltage slope V/s Table 7. V CC - Output Diode Symbol VF Parameter Forward on Voltage Test Conditions -IOUT =0.5A; Tj=150C Min Typ Max 0.6 Unit V Table 8. Status Pin Symbol VSTAT ILSTAT CSTAT VSCL Parameter Status Low Output Voltage Status Leakage Current Status Pin Input Capacitance Status Clamp Voltage Test Conditions ISTAT= 1.6 mA Normal Operation; VSTAT= 5V Normal Operation; VSTAT= 5V ISTAT= 1mA ISTAT= - 1mA 6 6.8 -0.7 Min Typ Max 0.5 10 100 8 Unit V A pF V V 4/15 VND810PEP-E ELECTRICAL CHARACTERISTICS (continued) Table 9. Logic Input Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage IIN = 1mA IIN = -1mA VIN = 3.25V 0.5 6 6.8 -0.7 8 VIN = 1.25V 1 3.25 10 Test Conditions Min. Typ. Max. 1.25 Unit V A V A V V V Table 10. Protections (See note 1) Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Current limitation Turn-off Output Clamp Voltage Test Conditions Min. 150 135 7 15 20 3.5 5.5V Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 11. Openload Detection Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A VIN=0V 1.5 2.5 Min 20 Typ 40 Max 80 200 Unit mA s V s 3.5 1000 5/15 VND810PEP-E Figure 5. OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT> VOL VINn VINn OVERTEMP STATUS TIMING Tj > TTSD VSTAT n VSTAT n tSDL tDOL(off) tDOL(on) tSDL Figure 6. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(on) dVOUT/dt(off) 10% t VINn td(on) td(off) t 6/15 VND810PEP-E Table 12. Truth Table CONDITIONS Normal Operation INPUTn L H L H H L H L H L H L H L H OUTPUTn L H L X X L L L L L L H H L H STATUSn H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOLn Output Current < IOLn Table 13. Electrical Transient Requirements on VCC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 I C C C C C C IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/15 VND810PEP-E Figure 7. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VCC VUSD VUSDhyst INPUTn OUTPUT VOLTAGEn STATUSn undefined OVERVOLTAGE VCC VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn OUTPUT VOLTAGEn STATUSn VOUT>VOL VOL OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj INPUTn OUTPUT CURRENTn STATUSn TTSD TR 8/15 VND810PEP-E Figure 8. Application Schematic +5V +5V +5V VCC Rprot STATUS1 Dld C Rprot INPUT1 OUTPUT1 Rprot STATUS2 Rprot INPUT2 GND OUTPUT2 RGND VGND DGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. 9/15 VND810PEP-E OPEN LOAD DETECTION IN OFF STATE Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL V batt. VPU VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2) GROUND 10/15 VND810PEP-E PowerSSO-12 Thermal Data Figure 10. PowerSSO-12 PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 78mm x 78mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2). Figure 11. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb(C/W) 70 65 60 55 50 45 0 1 2 3 4 5 6 7 8 9 PCB Cu heatsink area (cm^2) 11/15 VND810PEP-E Figure 12. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse ZTH (C/W) 100 Footprint 8 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 13. Thermal fitting model of a double channel HSD in PowerSSO-12 Pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Table 14. Thermal Parameter Area/island (cm2) R1/R7 (C/W) R2/R3/R8 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1/C7 (W.s/C) C2/C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.1 1.5 8 28 30 0.0001 0.0007 0.015 0.1 0.15 3 8 18 22 0.017 5 12/15 VND810PEP-E PACKAGE MECHANICAL Table 15. PowerSSO-12TM Mechanical Data Symbol A A1 A2 B C D E e H h L k X Y ddd 5.800 0.250 0.400 0 1.900 3.600 millimeters Min 1.250 0.000 1.100 0.230 0.190 4.800 3.800 0.800 6.200 0.500 1.270 8 2.500 4.200 0.100 Typ Max 1.620 0.100 1.650 0.410 0.250 5.000 4.000 Figure 14. PowerSSO-12TM Package Dimensions 13/15 VND810PEP-E REVISION HISTORY Table 16. Revision History Date Oct. 2004 Nov. 2004 Nov. 2004 Nov. 2004 Revision 1 2 3 4 - First Issue - PowerSSO-12 Thermal Charact. insertion - PC Board copper area correction - Thermal data correction. Description of Changes 14/15 VND810PEP-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 15/15 |
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